Prof. Shmuel Wimer

Our research team interests are in VLSI circuits and systems (CAS) design optimization and combinatorial optimization. The CAS activity covers a broad range of topics from transistors and interconnects, through computational circuits and embedded memories, up to micro-architecture. The team is cooperating with the domestic VLSI industry, the BIU EnICS Lab and Prof. Tsahi Birk at the Technion. The team is headed by Prof. Shmuel Wimer and comprises Mr. Binyamin Frankel, grad and 4th year undergrad students.

Our research team interests are in VLSI circuits and systems (CAS) design optimization and combinatorial optimization. The CAS activity covers a broad range of topics from transistors and interconnects, through computational circuits and embedded memories, up to micro-architecture. The team is cooperating with the domestic VLSI industry, the BIU EnICS Lab and Prof. Tsahi Birk at the Technion. The team is headed by Prof. Shmuel Wimer and comprises Mr. Binyamin Frankel, grad and 4th year undergrad students.

Shmuel Wimer is an Emeritus Professor with the Engineering Faculty of Bar-Ilan University. From 1978 to 2009 he held R&D, engineering and managerial positions in the industry. From 1999 to 2009 he was with Intel, and prior to that with IBM, National Semiconductor, and the IAI-Israel Aerospace Industry. He is with Bar-Ilan since 2009.

Binyamin Frankel received his B.Sc. and M.Sc. degrees in Electrical Engineering from Bar-Ilan University in 2014 and 2016, respectively. He is currently pursuing his Ph.D. degree in Computer Engineering at Bar-Ilan University. He is interested in VLSI circuits and systems design optimization.

We presently conduct two projects:

  1. 1. Gain-cell based branch predictor (BP). Whereas BP is a well-established microarchitecture feature, recent machine learning (ML) techniques suggest new implementations that may reduce misprediction rate considerably. However, ML-based BP techniques demand huge memory arrays, which similarly to other near-processor memories are implemented by SRAM. On the other hand, today’s low and ultra-low power processor design pursue the reduction of the supply voltage deeply below 1volt, where SRAM stops functioning reliably.
  2. A gain-cell eDRAM replacement has been proposed, but being a dynamic memory it must be somehow refreshed to avoid data destruction over tome. Fortunately, unlike near-processor storage holding instructions and data (e.g. L1 caches), whose contents destruction is catastrophic, errors in BP storage are not, but may rather lead to misprediction, translated to performance loss. This is where our project is targeting: exploring the relation between the dependence of prediction quality on the BP memory size on one hand, and refreshing / no refreshing and data retention time (DRT) on the other hand.
  3. Regarding DRT, we recently proposed to replace the GC by a tristate inverter based bit-cell, which leakage mechanisms could extend its DRT significantly. This may reduce the misprediction charged to data loss in the BP memory.
  1. 2. Deeply-fused pipelined dot-product (DFDP) multiplier. Dot-product multiplication is a common CPU-intensive operation used by many applications. To this end appropriate accelerators were proposed, replacing the iterative multiply-accumulate (MAC) computation scheme with a single-cycle operation, enabled by a DFDP multiplier. DFDP is a huge piece of hardware, and as such it is suspect to huge area increase (long wires, repeaters) if long vectors of wide words are aimed at. Such acceleration by a single-cycle implementation reaches a delay limit, leading naturally to pipeline implementation.
  2. Our research explores the relations between the pipeline depth and the performance measures such as speed, power and energy. Clearly, pipeline is also limited and at a certain depth improvement will stop. So another research question is where this point is. Results for a 65nm DFDP multiplier for 16-element vectors of 16-bit words showed that beyond depth three no speedup is achievable.

Contact details

Prof. Shmuel Wimer

email: wimers@biu.ac.il

phone (office): +972-3-5317208.

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