The Computer Architecture Lab, in the School of Electrical Engineering, Tel Aviv University, performs research in microarchitecture, multicore, multithreading, low power, RISC V, and code compaction. The research group is led by Prof. Shlomo Weiss and currently consists of six MSc with thesis students and one PhD. The lab is managed by Mr. Roger Kahn, who coordinates the Genpro research tasks and is responsible for the computer systems and software tools required for research.
In the framework of the GenPro Consortium our research is performed by the PI (Prof. Shlomo Weiss), three MSc students (Stephan Chulski, Shai Mikler and Fadi Majdalani), and one MSc electrical engineer (Roger Kahn). In collaboration with Mellanox, Bar-Ilan Enics Lab, and Dolphin we work on three tasks described below.
- 1. Multithreaded processors
- The objective of a multithreaded processor is to improve performance. Simultaneous Multithreading (SMT) is a well known MT method. We are interested in investigating other MT methods that may provide acceptable performance at lower cost or power for embedded processors.
- 2. History based prefetching in RISC V
- History based prefetching is a promising method that has not been implemented in RISC V. We propose to implement and analyze history based prefetching and to integrate it with a low power RISC V core at the RTL level.
- 3. Hybrid cache memory design
- In a hybrid cache the tag and data arrays are implemented with different technologies. Our goal is to investigate performance, cost, and power tradeoffs in hybrid caches.
Prof. Shlomo Weiss, email@example.com