Prof. Joseph Shor

Prof. Joseph Shor is one of the only academic researchers in Israel who specializes in Analog Design. His specialties include Power Management, Sensors, Analog Circuits for Microprocessors, Ultra-Low Power Analog, Hardware Security and Clocking. Prior to Bar Ilan, he was a > 20 year veteran of the Israeli High Tech. His last position was Principal Engineer at Intel where he led an analog team in the Microprocessor Division. He presently leads a team of 12 Ph.D and M.S Students, some of whom are experienced Engineers in Israeli High Tech companies, such as Intel, Microsoft, Mellanox, Apple and others. He is a member of the ENICs lab. He holds over 50 patents and pending patents and has published over 60 technical papers. For more information see the personal website –

For the Genpro consortium, we proposed a novel Vth detection circuit which will be used for the Vdd regulation. We intend to design this circuit for fast conversion (10us), such that it can be activated quickly when the chip exists from deep-sleep states. It will also be used as the reference voltage either for the external Voltage Regulators (VR) or for an on-die VR.

The Genpro consortium is very interested in multi-core operation of RISC-V and this is a key feature of this architecture (4, 16 or possible even more cores). In order for each core to operate at an optimal energy point, it is crucial to have a functional dynamic voltage scaling (DVS). An on-die LDO (Low Dropout Regulator) will enable this operation. A highly loaded core can operate at high performance at high voltage, while another core’s Vdd is regulated to near-Vth to optimize energy efficiency while it functions at a lower workload. Furthermore, we intend to design this L DO such that it can correct Vdd droops which are caused by current surges.

By the end of the consortium, we will have a power management solution which will enable Near-Vth operation of RISC-V elements in an efficient manner. This will be accomplished by accurately measuring Vth on die and using this information to regulate either external or internal VR’s. At the successful conclusion of this research, we will enable dynamic voltage scaling (DVS) per core. Multi-core operation at different voltage levels will be possible, such that one core can operate at maximum load and maximum Vdd, while another core operates near-Vth at a lower performance, but higher efficiency voltage level.

Contac: Prof. Joseph Shor,