Prof. Alexander Fish is a Professor in the Faculty of Engineering at Bar-Ilan University and he is a founder and head of the Emerging nanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center.
His research team includes students, engineers and postdoctoral fellows working on power reduction methodologies for high speed digital and mixed signal VLSI chips, energy efficient embedded memory arrays, CMOS image sensors, biomedical circuits, systems and applications, quantum circuits and hardware security. As the head of the EnICS Labs impact Center, Prof. Fish is involved in many aspects of the GenPro project, including the embedded core development and SoC integration and implementation.
The target of Prof. Fish’s group in the GenPro project is to improve the performance and the power consumption of RISC-V core by utilizing the advantages of the Dual Mode Logic gates family that was proposed by Prof. Fish’s team.
The unique capability of Dual Mode Logic (DML) to alternate between static and dynamic modes at run-time enables the integration of both high speed and low energy data paths as a function of system requirements. At the gate level, two different working modes can be selected (either static or dynamic) to change the power/performance characteristics of the circuit. The static mode aims to save energy consumption when speed constraints are relaxed, whereas in the dynamic mode the DML gates achieve high speed at expense of higher energy consumption.
GenPro project enables the first examination of the DML technology in the full environment of the RISC-V processor. Prof. Fish’s group is working on implementing the technology to achieve several important goals: First, to improve the performance of the Arithmetic Logic Unit (ALU) of the core by implementing different blocks; for example DML multiplier can operate faster than standard logic. Second, to expand the performance of the memory subsystem by operating the circuits in the dynamic mode whenever critical access to the memory is detected. This is done in close collaboration with Dolphin Integration. The third goal is to improve the robustness of the system to process variations to reach higher operational frequency.
Another target of Prof. Fish’ s group is to make DML suitable for standard design flow. DML was proven to be very efficient in custom design. However, implementing DML using automated design tools and standard flow is a very challenging task. In the GenPro project, Prof. Fish’s team in collaboration with industry is exploring the methodology for implementing the logic family using the standard tools and flows. Success in this task will be a breakthrough in terms of the DML technology as it will allow the design of complex and large modules in a much simpler and much shorter time.
Prof. Alex Fish, Alexander.Fish@biu.ac.il