State of the art chip design requires a substantial amount of innovation and research in order to provide advances in computational capabilities for cutting edge applications. Chip Design is a complex operation, requiring experienced engineers, extensive and diversified knowledge, as well as advanced infrastructure and methodologies. To meet these challenges, we have established the EnICS SoC lab. The SoC lab aims to bridge the gap between academic research and industrial applications and requirements by enabling to turn research ideas into a proof of concept. This model is unique in Israel, and possibly in the entire world, in its scope and expertise.
The SoC lab engineering team master all aspects of chip design, form architecture definition through logic integration, functional verification, backend integration and physical signoff to silicon validation. The team has designed and implemented industry-class integrated circuits in advanced technologies, the recent one in 16nm process technology.
Yehuda Rudin, General Manager, joined the lab after 28 years with the Freescale Semiconductors Design Center. There he defined and designed some of the company’s most successful Digital Networking products, rose to the role of General Manager and won recognition as a Freescale Fellow.
Yonatan Shoshan, Design Manager, joined the lab after 8 years of work in semiconductor companies, startups as well as well-established global companies such as Texas Instruments. Yonatan is leading the SoC lab design team.
Yehuda (Udi) Kra, Chief Architect, brings with him extensive and versatile design experience from the industry, most recently with SatixFy, including the startup arena. Udi is currently driving the RISC-V design activities.
Dr. Yoav Weizman, Engineering Leader, manages the silicon validation activities of the lab, as well as reliability aspects. Yoav worked for 12 years with Freescale Semiconductor, in the area of failure analysis and device characterization.
The Bar-Ilan SOC lab serves as the central design center of the GenPro consortium. The charter of the lab is to define the architecture of a RISC-V processor core optimized for embedded applications, to implement it as well as a RISC-V processor core targeted for high-throughput applications. In addition, the lab will design an advanced multi-core SOC that will integrate the processor cores for evaluation, testing, functionality demonstration and as a reference design for future commercial products.
In this role, the lab collaborates closely with all members of the consortium form industry and academia and in particular with Mellanox, that is responsible for the definition of the high-throughput processor core.
In the framework of GenPro consortium, the ultimate goal of the Bar-Ilan SOC lab is to eventually become a RISC-V center of excellence for the Israeli semiconductor industry, sharing, assimilating and expending the knowledge for the benefit of Israeli industry.
Name: Yehuda Rudin
Telephone (office): +972-3-5317039