Dr. Adam Teman is a senior faculty member in the Faculty of Engineering at Bar-Ilan University and a co-director of the Emerging nanoScaled Integrated Circuits and Systems (EnICS) Labs Impact Center.
Dr. Teman’s research spans digital VLSI design from the device modelling level up to the system design level, with his specialty focused on digital circuit design, and specifically, embedded memory design. His research team includes students working on novel embedded memories, advanced techniques for physical implementation of integrated circuits, hardware for artificial intelligence, RISC-V based architectural enhancements and more. In the framework of GenPro, Dr. Teman’s group is a core participant in the memory subsystem definition committee and its main task is the development of custom register files for RISC-V cores in close collaboration with Dolphin Integration. In addition, Dr. Teman’s group is developing advanced methods for inner-level caching and techniques for controlled placement of register files. As co-director of EnICS Labs, Dr. Teman himself is involved in almost all aspects of the GenPro project, focusing on the embedded core development and SoC integration and implementation.
The main task of Dr. Teman’s research group in the GenPro project is the implementation of custom register files for the RISC-V cores. This task is carried out in close collaboration with Dolphin Integration and based on the specifications defined by the memory subsystem committee and the requirements of the high-performance and low-power cores. In addition to Dolphin Integration, these specifications were defined in close collaboration with Mellanox and the EnICS SoC Lab.
The ultimate goal of the register file research is to create a framework for generating a spectrum of small embedded memory blocks to meet the various requirements of the GenPro project. There is a large spectrum of specifications, from very high-speed registers to ultra-low power memories; from high-density single-ported arrays to ones with multiple access ports enabling scan integration and reset capabilities; and more. The vision is to provide a push-button tool, in which the platform architect will input their requirements and the tool will provide the perfect memory block to meet the specification, including all required views for full flow integration.
As a first step towards achieving the ultimate goal, described above, Dr. Teman’s team is partnered with Dolphin Integration in designing a register file that integrates many of the more complex features of the overall, broad specification. This block is an ultra-high speed content-addressable array including support of scan integration and column-wise reset. The block is intended for integration in the highly-associative table lookaside buffer (TLB) of the high-performance core and is targeted at over 2 GHz operation in a 16nm FinFET process. This extremely challenging goal includes design from the specification level, through block architecture, circuit design, custom layout, functional and physical verification, and eventually, compiler support for modular automatic generation.
Name: Dr. Adam Teman
Telephone (office): +972-3-738-4476