Headquartered in France, Dolphin Design, previously known as Dolphin Integration, is a semiconductor company employing 160 people, including 140 highly qualified engineers.

Their IP clusters, available for various technological processes and optimized for the best Energy Efficiency, feed their tailored, scalable and modular Power Management and MCU subsystem platforms to deliver fast and securely ASICs, either designed by or for their clients.

By the side of their clients, now exceeding 500 companies, they focus on human, inventive and long-term collaboration to enable them to bring products and devices, powered by innovative and accessible integrated circuits that minimize environmental impact, to the hands of billions of people everyday. In consumer markets including IoT, AI and 5G, or in high reliability markets, they unleash SoC designer creativity to deliver differentiation.

Dolphin Integration Ltd is the fully owned subsidiary of Dolphin Design. It has been established in October 2009 in Netanya, Israel, and employs currently 6 engineers. It is specialized on designing flexible, dense and ultra-low power SRAM memory & register-file architectures, from 130nm down to 22nm, in both bulk-CMOS and FDSOI technologies.

In 2015, the Israeli team was granted US Patent 9,269,423 B2 (as well as French & UK patents) for a novel latched-based register file, which is now being implemented as part of the GENPRO consortium.

In 2016, Dolphin engaged in activity in the field of hardware security developing countermeasures for side-channel attacks over memories, as well as advanced fault-detection codes together with the Bar-Ilan university in Israel, under the Israeli Authority of Innovation’s “Magneton” framework.

The subsidiary had also been active in other novel technologies such as activities in the field Radiation-Hard memories and more.

Dolphin-Integration Ltd is ISO-9001 qualified since 2011 and TSMC IP-9000 qualified since 2012

As part of GenPro, Dolphin Integration Ltd. shall define, characterize & develop novel memory architectures with exceptional performance, tailored to the needs of the processor developed by the members of the consortium, which would enable the performances defined by the initiators of the consortium in terms of frequency, power consumption and multi-core/multithread operation. In addition, Dolphin shall lead the memory-subsystem workgroup.

Primary Goals:

Design a Register-File / LUT architecture optimized for meeting the performances of the RISC-V Processor

The novel register-file would seamlessly replace a synthesized register-file using Flip-Flops or Latches inside RTL designs

  • Asynchronous read operation, multi read ports
  • Extremely high speed read access – For applications such as Look-Up-Table, Cache Tag memory etc
  • Synchronous write operation, multi write ports
  • Advanced low-power modes for embedded RISC-V cores.
  • Unique custom features for RISC-V cores and memory subsystems.
  • Area Goal : < ½ of Flip-Flop-based
  • Easy to use approach:
    • RTL : Fully compatible, seamless replacement
    • BE : Macro-Cell approach integrable within a logic sea-of-gates
    • Reset function (Unlike SRAM-based)
    • Scan chain (Unlike SRAM-based)
  • Main achievements of the first period (18 months):
    • Definition of the specifications for the novel memory architecture
    • Completion of schematic design & simulations
    • Completion of layout of all basic leaf-cells towards the start of memory compiler integration
    • Design of the memory subsystem for both processor configurations – “Performance” and “Embedded” (Leading the memory subsystem workgroup)

Contact details:

Ilan SEVER, Subsidiary General Manager

Dolphin Integration Ltd

7 Giborey Israel St, Poleg Ind. Zone, Netanya South


Phone : +972-73-7374350

Mailto :